Amazing MEMS

Next Generation KGD Memory Test Achieved Wafer Level Speed Beyond 3GHz | Lee
Presented at TestVision 2021

Recent industry wide adoption of heterogeneous integrated system enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die (KGD) and known-good-stacked-die (KGSD). Coupled with the advancement on DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory is running beyond 2GHz (4Gbps) which is pushing the limit on existing ATE testers. Recent joint effort between SK Hynix, FormFactor, and Advantest successfully demonstrated that beyond 3GHz is achievable. This session discusses the design challenges overcame in this collaboration from a system level signal integrity and power delivery perspective.

Digital Revolution: PAM4 Wafer Test | Raschko
Presented at TestVision 2021

As data rates continue to increase, the difficulty of increasing clock rates for improved bitstreams becomes more challenging with ever-increasing loss. As of today, Non-Return-to-Zero (NRZ) is the standard for digital encoding, but this begins to run into problems with loss and the collapse of the digital eye beyond 40 Gbps. To counter this, Pulse Amplitude Modulation 4-Level (PAM4) is beginning to emerge in digital communications which allows for the same fundamental frequency to be used as NRZ while doubling the data rate by introducing two additional amplitude levels to the traditional 2-level encoding. This paper will address the implications of this change for wafer test and will explore the sensitivity of PAM4 to different types of loss along with how this loss can be countered in the probe card.

5G: The Phanerozoic Eon of Parallelism | Bock
Presented at TestVision 2021

5G has been pushing on wafer test of several years now and the test cell is evolving to more complex systems.  Same as the change to multicellular life during the Phanerozoic Eon, we are seeing a concerted change to multi-DUT testing with 5G parts in order to improve the output from manufacturing wafer test.  Now, 5G is in the middle of ramp, with more handsets being released with 5G FR2 chipsets being released. Current estimates put up to a 150.7% CAGR increase in the number of devices with 5G from now until 2024.  This growth requires a subsequent increase in the wafer test capability in the manufacturing flow to provide Known Good Die (KGD) in a reasonable cost of test.  There are multiple ways to increase the volume and minimize cost of test.  Some of these include more test cells, but buying more testers is can become cost prohibitive. Another strategy is to provide more test parallelism with upgraded testers that have mW frequency capability with a low number of channels in the tester, but resources are extended by using switches and other types of channel count increase.  Another method is to use wafer loopback test, but that reduces the test visibility due to the signals never getting back to the tester.  All of these have advantages and drawbacks.  We will discuss multiple ways to do this as well as discuss the Cost of Ownership Implications.

The Digital Revolution: NRZ to PAM4 | Bock, Raschko
Best Overall Presentation - SWTest 2021

With increasing demand to process more data and pass large amounts of data through servers, cellular devices, and even within the computer for the highest performing video cards, the need for more complex digital processing is becoming greater than ever. In this presentation, Daniel Bock and David Raschko will show some of the impacts of NRZ compared to PAM4 on wafer test through example probe cards and describe the changing test requirements.

Next Generation KGD Memory Test Achieved Wafer Level Speed Beyond 3 GHz/6 Gbps | Liao
Presented at SWTest 2021

Recent industry wide adoption of heterogeneous integrated system enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die. Coupled with the advancement on DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory is running beyond 2 GHz (4 Gbps) which is pushing the limit on existing ATE testers. Recent joint effort between SK Hynix, FormFactor and Advantest successfully demonstrated that beyond 3 GHz is achievable. This session discusses the design challenges overcame in this collaboration from a system level signal integrity and power delivery perspective.

Next Generation SmartMatrix Probe Card Technology Enables 3000-Parallelism 1TD Test for 1Z DRAM Process Node | Ceremuga
Presented at SWTest 2021

The DRAM technology process node continues to shrink, driven by the demand to increase bit density and reduce memory device cost. With the recent accelerated transition from the 1Y to 1Z process node, die count per wafer is increasing rapidly. Wafer sort throughput must advance to achieve the target cost without adding significant capital expenditure to the existing test floor. Samsung and FormFactor have been working together, and successfully developed and qualified the next generation DRAM probe card that leverages FormFactor’s ATRE technology for 3000-parallelism and beyond. FormFactor’s SmartMatrix 3000XP probe card enables remarkable high-parallelism test throughput by extending ATE tester resource sharing up to X32. This session discusses the key technology enablers of the SmartMatrix 3000XP product architecture, and the design challenges overcame during this successful collaboration.

Challenges of Expanding Large Area Active Array for Fine Pitch Vertical Probe Cards | Harker, Desta
Best Data Presentation - SWTest 2021

Semiconductor manufacturers are on a relentless drive to reduce the total cost of test at sort. A major contributor to reducing cost of test is increasing simulations Device Under Test which requires a subsequent increase in the probe card active area. FormFactor has developed a new probe card architecture to address the challenges of fine pitch, high CCC, and high temperature range for wire bond probing applications.